74LVC02AD,118

74LVC02AD,118 is a quad-input NOR gate. This device inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V applications. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. It complies with JEDEC standard (JESD8-7A (1.65V to 1.95V), JESD8-5A (2.3V to 2.7V), JESD8-C/JESD36 (2.7V to 3.6V). It also features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 3.6V, overvoltage tolerant inputs to 5.5V
• CMOS low power consumption, direct interface with TTL levels
• Input leakage current is ±0.1μA typical at (VCC = 3.6V; VI = 5.5V or GND, -40°C to +85°C)
• Supply current is 0.1μA typical at (VCC = 3.6V; VI = VCC or GND; IO = 0A, -40°C to +85°C)
• Input capacitance is 4pF typical at (-40°C to +85°C
• Propagation delay is 14ns typical at (VCC = 1.2V, -40°C to +85°C)
• Output skew time is 1ns maximum at (VCC = 3.0V to 3.6V, -40°C to +85°C)
• Power dissipation capacitance is 2.5pF typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• SO14 package

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